Tabula ABAX and the Evolution of 3D Programmable Logic
In the pursuit of higher density and faster processing for programmable hardware, Tabula introduced a revolutionary approach to integrated circuits. By moving beyond traditional two-dimensional architectures, the company developed the ABAX family, which they categorized as 3D programmable logic devices (3PLDs). These devices aimed to bridge the gap between the flexibility of Field-Programmable Gate Arrays (FPGAs) and the performance of dedicated hardware.
Key Facts
- Product Line: ABAX family of 3D integrated circuits (3PLDs).
- Performance: Physical clock speeds of up to 1.6 GHz.
- Capacity: 220,000 to 630,000 4-input lookup tables (LUTs).
- Manufacturing: Produced using 40 nm TSMC and later 22 nm Intel processes.
- Connectivity: Up to 920 GPIO pins and 48 SerDes channels (6.5 Gbit/s).
- Company Status: Officially shut down on March 24, 2015.
The ABAX Architecture: Redefining the FPGA
The ABAX chips were designed to provide a massive amount of logic resources within a compact footprint. From a user perspective, these chips offered between 220,000 and 630,000 lookup tables (LUTs)—the basic building blocks used to implement combinatorial logic in programmable devices. To support high-performance computing, they integrated up to 1,280 digital signal processing (DSP) blocks featuring 18x18 multipliers with pre-adders.
Physical connectivity was a core strength of the ABAX line, featuring up to 920 general-purpose input/output (GPIO) pins and 48 SerDes (Serializer/Deserializer) channels capable of speeds up to 6.5 Gbit/s. These chips were housed in flip-chip packages with either 1,156 or 1,936 pins.
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The Concept of "Folds" and Time-Multiplexing
The secret to the ABAX's high capacity was its internal use of high-frequency reconfiguration. The chips operated at a physical clock speed of 1.6 GHz, switching between up to eight configuration states known as folds. This allowed the device to emulate a much larger number of FPGA resources than physically existed on the silicon.
There was a direct trade-off between capacity and speed: if all eight folds were utilized to maximize LUT capacity, the user-visible clock speed dropped to 200 MHz. Conversely, using only four folds halved the capacity but doubled the effective frequency.
Manufacturing and Market Positioning
Initially produced using the 40 nm TSMC process, Tabula expanded its manufacturing capabilities in February 2012 by confirming a move to Intel's 22 nm process. At the time, Tabula was one of only five companies permitted to use Intel's manufacturing process, alongside Achronix, Netronome, Microsemi, and Altera.
In 2012, the company planned for volume pricing of ABAX chips to range between 100 and 200 USD. Beyond the core 3PLD chips, Tabula offered specialized network solutions, including high-speed packet search engines, multiport 10 gigabit Ethernet processors (suitable for routers, switches, or programmable NICs), and bridges connecting 40 or 100 Gb Ethernet to Interlaken.
Spacetime: Beyond Traditional FPGAs
Tabula also developed a product called Spacetime, which sought to transcend the limitations of standard FPGAs. Spacetime utilized a unified 3D framework that integrated two spatial dimensions and one time dimension. This innovation was intended to create a new category of programmable devices that were denser and faster than FPGAs, while still utilizing software that could automatically map traditional Register Transfer Level (RTL) designs onto the novel 3D fabric.
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| Feature | Specification |
|---|---|
| LUT Capacity | 220k - 630k (4-input) |
| Physical Clock Speed | 1.6 GHz |
| DSP Blocks | Up to 1,280 (18x18 multipliers) |
| SerDes Channels | 48 channels (up to 6.5 Gbit/s) |
| GPIO Pins | Up to 920 |
| Manufacturing Processes | 40 nm (TSMC), 22 nm (Intel) |
Frequently Asked Questions
What is a 3PLD?
A 3PLD, or 3D Programmable Logic Device, is a type of integrated circuit developed by Tabula that uses a three-dimensional framework (incorporating time as a dimension) to achieve higher density and performance than traditional 2D FPGAs.
How did the "folds" system work in ABAX chips?
The chips used high-frequency reconfiguration to switch between up to eight different configuration states, or folds. This allowed the hardware to emulate more logic resources (LUTs) than were physically present, though increasing the number of folds reduced the user-visible clock speed.
What was the relationship between Tabula and Intel?
Tabula was one of only five companies authorized to use Intel's 22 nm manufacturing process as of July 2013.
What was the purpose of the Spacetime product?
Spacetime was designed to be a denser and faster alternative to FPGAs by unifying two spatial dimensions and one time dimension into a single framework, while remaining compatible with traditional RTL software mapping.
When did Tabula cease operations?
Tabula officially shut down on March 24, 2015.