Amber Core: Open-Source ARMv2a FPGA Implementations
The Amber project provides a sophisticated set of open-source processor cores designed specifically for field-programmable gate array (FPGA) synthesis. By leveraging the ARMv2a instruction set, the Amber core offers a patent-free implementation of the ARM architecture, allowing developers to build embedded systems without requiring a license from ARM Holdings. Developed using Verilog 2001, these cores are optimized for efficiency and seamless integration into FPGA environments.
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To ensure a complete ecosystem, the Amber project does not just provide the CPU core; it offers a full embedded FPGA system. This system integrates the core with essential peripherals, including timers, universal asynchronous receiver/transmitters (UARTs)—which handle serial communication—and an Ethernet MAC for network connectivity.
Key Facts
- Architecture: Fully compatible with the ARMv2a instruction set.
- Toolchain: Supported by the standard GNU toolchain.
- Optimization: Designed for FPGA synthesis with no dedicated reset logic, relying instead on FPGA initialization.
- OS Support: Verified with Linux 2.4 kernel; supports non-virtual memory variants like μClinux.
- Interface: Both core versions utilize the Wishbone interface.
Comparing the Amber 23 and Amber 25 Cores
The Amber project offers two distinct versions of the core. While both share the same Instruction Set Architecture (ISA) and are fully software compatible, they differ significantly in pipeline depth and performance.
Amber 23: The Compact Performer
The Amber 23 is a small 32-bit core featuring a 3-stage pipeline and a unified cache for both instructions and data. It delivers a performance rating of 0.75 DMIPS (Dhrystone MIPS) per MHz. In this model, register-based instructions typically execute in a single cycle, with the exception of multiplication. Load and store operations require three cycles. The pipeline stalls during Wishbone accesses or when a cache miss occurs.
Amber 25: The High-Efficiency Alternative
The Amber 25 is designed for higher throughput, utilizing a 5-stage pipeline and separate caches for data and instructions. This architecture allows it to achieve 1.0 DMIPS per MHz, representing a 30% to 40% performance increase over the Amber 23, though it requires 30% to 40% more area. Most instructions, including load and store, execute in one cycle, unless there is a register conflict with a subsequent instruction, a complex shift operation, or a multiplication. Pipeline stalls occur during cache misses, instruction conflicts, complex shifts, or Wishbone accesses.
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| Feature | Amber 23 | Amber 25 |
|---|---|---|
| Pipeline Stages | 3-stage | 5-stage |
| Cache Architecture | Unified | Separate (Instruction/Data) |
| Performance | 0.75 DMIPS/MHz | 1.0 DMIPS/MHz |
| Load/Store Execution | 3 cycles | 1 cycle (unless conflict) |
| Relative Size | Baseline | 30% to 40% larger |
Operating System and Software Compatibility
Both the Amber 23 and 25 cores have been verified by successfully booting a Linux 2.4 kernel. Because these cores lack a Memory Management Unit (MMU)—the hardware component responsible for translating virtual addresses to physical addresses—they cannot run standard virtual memory Linux. Instead, they are designed for non-virtual memory variants, such as μClinux.
While the 2.4 branch of the Linux kernel contains native configurations for the ARMv2a ISA, users attempting to use Linux kernel 2.6 or later will find that explicit support for ARMv2a has been removed, necessitating further modifications to the kernel to achieve compatibility.
Frequently Asked Questions
Why was the ARMv2a instruction set chosen for the Amber core?
The ARMv2a instruction set was selected because it is not covered by patents, allowing the Amber core to be implemented as an open-source project without requiring a license from ARM Holdings.
What is the difference in performance between Amber 23 and Amber 25?
The Amber 25 provides 30% to 40% better performance than the Amber 23, reaching 1.0 DMIPS per MHz compared to the Amber 23's 0.75 DMIPS per MHz.
Can the Amber cores run a standard version of Linux?
No, because the cores do not have a Memory Management Unit (MMU), they can only run non-virtual memory variants of Linux, such as μClinux.
How is the reset logic handled in these FPGA cores?
The cores are optimized for FPGA synthesis and do not contain explicit reset logic; instead, all registers are reset during the standard FPGA initialization process.
Which toolchain is used to develop software for the Amber core?
The Amber core is fully supported by the GNU toolchain.